In the semiconductor industry, Moore's law states that the number of transistors on a chip doubles approximately every two years. These exponential performance gains present a challenge to the semiconductor manufacturing industry, along with the dual challenges of promoting power savings and providing cooling efficiency. The industry faces these challenges in multiple ways. Reducing gate height can reduce gate capacitance and increase device performance. Furthermore, gate height is limited by the requirement of source/drain ion implantation steps due to reducing space between gate electrodes. In a gate-first process flow, the minimum gate height is limited by the need to remove the cap nitride layer on top of the polysilicon or a-Si prior to the silicidation process. Since a nitride spacer will be etched together with the cap nitride layer during the cap nitride removal etch with essentially no selectivity, too short a gate (which implies a short spacer) will lead to complete spacer removal and damage to the high-k metal gate. The unprotected metal gate is susceptible to damage from chemistry in cleaning steps, or oxygen could diffuse into the high-k metal gate and change the Vt (voltage) of the devices. This problem is exacerbated by the inherent differences in topography between the silicon substrate and STI, and furthermore the source/drain process differences on different types of transistor devices on the same wafer.
Referring now in specific detail to the drawings, and particularly to FIGS. 1A, 1B, and 1C, there is provided an illustration of a gate patterning process, according to the known art. These TEM images show the progression of the gate profile through the gate patterning process steps. FIG. 1A shows a typical gate profile after silicon nitride (SiN) hard mask reactive ion etching (RIE). The arrow of FIG. 1A points to the inherent topography differences between the silicon substrate and the STI. FIG. 1B shows a typical gate profile after the polysilicon etch step. FIG. 1B illustrates the height difference for gates over silicon and polysilicon wires over STI clearly.
FIG. 1C shows a typical gate profile after the completion of high-k/metal gate etch. The cap nitride is essentially intact. FIG. 1C also illustrates the relative proportion of polysilicon and cap nitride heights in a typical state-of-the-art semiconductor process technology using a high-k metal gate.
FIG. 2A shows the spacer/encapsulation to silicidation process sequence according to the known art. Starting from the finished gate at the left (same image as in FIG. 1C), the typical gate goes through first spacer nitride deposition and etch on the p-type transistor region (second and third images), source/drain ion implantation steps, embedded SiGe etch/growth in the p-type transistor region, cap nitride removal etch, and silicidation. As a result of limited starting height of the spacer nitride, starting topography, and the multitude of etch steps the wafer is subjected to, only a small amount of nitride spacer is left for some gates to separate the gate from the source/drain region at the silicidation step in the known art. This lack of nitride separation causes yield loss and increased defect level on the wafer. FIG. 2B shows the difference in cap nitride thickness due to different process flows on n-type transistor and p-type transistor by an example. The example process includes embedded SiGe source/drain to enhance the performance of the p-type transistor by applying stress to the channel region. In this example process flow, the p-type transistor is subjected to an additional etch step to create the cavity in the source/drain region. This cavity etch can erode the cap nitride layer significantly, by as much as half of its starting thickness.
FIG. 3 shows the cap removal process, specifically typical gate profiles for excessive cap nitride RIE or overly conservative cap nitride RIE. FIG. 3 shows that if the cap nitride RIE is too much, the spacer nitride will be etched too much and some gates will be damaged or some gates will have an electric short to the source/drain region. If the cap nitride RIE is not enough to clear all the cap nitride from all gates, some gates will fail to form silicide, which leads to high resistance spots and circuit failure. The process window is determined with the initial gate height as compared to the variation in cap nitride top surface level caused by topography and different process history on different devices.